A peripheral component interconnect express (Peripheral Component Interconnect Express, abbreviated as PCI express) provides a fast point-to-point serial communication link for a PCI express device. While providing sufficient bandwidths for data-intensive applications such as multimedia and high-speed local area networks, the PCI express is confronted with a link energy management problem.
Power consumption in a PCI express link increases as the bandwidth of the link increases, while the bandwidth of the link is associated with a transmission rate and bit width of the link. When traffic in the link is low, a high bandwidth is not necessary, and the bandwidth of the link can be reduced by lowering the transmission rate or bit width of the link, thereby reducing the power consumption of the link. When the traffic in the link rises, the bandwidth of the link is increased by increasing the transmission rate or bit width of the link, so as to satisfy a service requirement of the link. Therefore, energy management of the link can be implemented by adjusting the rate and/or bit width of the link. In the prior art, a PCI express device may control migration of a physical layer state machine according to a traffic volume in the link, and adjust the rate or bit width of the PCI express link by controlling the migration of the physical layer state machine, thereby implementing the link energy management according to the traffic volume. Specifically, when the traffic volume in the link changes, the PCI express device controls its physical layer state machine to enter a recovery state from a normal working state, namely, interrupting current data sending and receiving in the link and entering configuration state. In the configuration state, the PCI express device can obtain a required bandwidth by adjusting the rate or bit width of the link, thereby implementing energy management of the PCI express link.
However, in the above PCI express link energy management process, when the physical layer state machine enters the recovery state from the normal working state, the PCI express device interrupts current data sending and receiving in the link, which results in loss of data being sent and received currently.